In many memory applications, SONOS memory transistors and conventional CMOS devices are fabricated on a single semiconductor wafer. Typically, the CMOS devices are fabricated in a first region of the wafer, while the SONOS memory transistors are fabricated in a second region of the wafer. On some wafers, the SONOS memory transistors are fabricated as part of a fieldless array. A fieldless array is defined as an array that does not use field oxide or shallow trench isolation (STI) to isolate the various elements of the array. Because field oxide and/or STI is not required to isolate the SONOS memory transistors in a fieldless array, the SONOS memory transistors can be laid out with a relatively high density.
In certain applications, conventional CMOS devices (e.g., transistors) are fabricated in the second region, but do not form part of the fieldless array. That is, the CMOS devices located in the second region are isolated by field oxide. Thus, the second region can include both SONOS memory transistors and CMOS devices.
In order to distinguish the above-described transistors, the following nomenclature will be used. As used herein, the term “fieldless array transistor” refers to a floating gate SONOS type non-volatile memory transistor that is used to form a fieldless array. A fieldless array transistor does not require field oxide or STI isolation. Each fieldless array transistor can store one bit or multiple bits in a manner known to those of ordinary skill.
As used herein, the term “logic transistor” refers to a transistor fabricated in accordance with conventional CMOS processes, regardless of whether the transistor is fabricated in the first region or the second region of the semiconductor wafer. A CMOS logic transistor is isolated from other elements by field oxide or STI. CMOS logic transistors can further be classified as low voltage (e.g., 1.8 Volt) CMOS logic transistors, medium voltage (e.g., 3.3 Volt) CMOS logic transistors and high voltage (e.g., 8-10 Volt) CMOS logic transistors, in view of the operating voltages applied to the logic transistors. Note that the high voltage CMOS logic transistors are required to access the fieldless array transistors. Thus, a high-voltage oxide (e.g., 150-200 Angstroms) must be fabricated in the first region in addition to low voltage oxide (e.g, about 30 Angstroms) and medium voltage oxide (e.g., about 70 Angstroms). The higher the voltage to be handled by the CMOS logic transistor, the thicker the required gate oxide of the transistor, thereby enabling the transistor to withstand higher gate voltages.
The process steps required to fabricate high, medium and low voltage CMOS logic transistors are not fully compatible with the process steps required to fabricate fieldless array transistors. For example, if thermal oxidation is used for fabrication of the high-voltage oxide, additional thermal budget is required. In addition, thermal oxidation of the high-voltage oxide will influence the shape of shallow trench isolation (STI) divots, and can enhance mechanical stresses in silicon. As a result, transistor and diode leakage currents will typically increase.
It would therefore be desirable to have an improved process for fabricating high, medium and low voltage CMOS logic transistors and fieldless array transistors on the same wafer.
FIG. 1 is a cross-sectional view of a conventional SONOS fieldless array transistor 100. Fieldless array transistor 100 includes p-type semiconductor substrate 101, N-type source/drain regions 102-103, oxide-nitride-oxide (ONO): memory stack 110, bit line oxide 114 and polysilicon gate electrode/word line 115. ONO memory stack 110 includes bottom silicon oxide layer 111, silicon nitride layer 112 and top silicon oxide layer 113. Source/drain regions 102-103 extend to other memory transistors, and operate as diffusion bit lines.
Bit line oxide 114, which provides isolation between the diffusion bit lines, is implemented by oxidizing the heavily implanted source/drain regions 102-103 between the patterned ONO stack 110. The isolating bit line oxide 114 is similar to LOCOS oxide. The thickness of bit line oxide 114 must be large enough to ensure no leakage between gate electrode/word line 115 and source/drain regions 102-103. Bit line oxide 114 typically has a thickness (T) of 500 to 1000 Angstroms to compensate for the relatively low quality of bit line oxide grown over N+ source/drain regions 102-103 (compared with the relatively high quality gate oxide of the same thickness grown over a p- substrate).
Fieldless array transistor 100 may exhibit low reliability because of problems associated with electrical weakness of ONO memory stack 110 at the locations where ONO memory stack 110 joins bit line oxide 114 (i.e., at the bit line oxide “oxybeaks”.) The oxybeak regions are labeled “OB” in FIG. 1. Bit line oxide consumption and influence on the edges of the top oxide layer 113 of ONO stack 110 during resist removal operations are strongly pronounced in embedded process flows. This results in poor dielectric performance in the oxybeak region and directly influences the reliability of the resulting memory device.
High-temperature CVD oxide has been used to form the top oxide layer of an ONO memory stack of a fieldless array transistor, thereby lowering the leakage of the ONO memory stack. (See, U.S. Pat. No. 6,265,268.) High-temperature oxide has also been used instead of an ONO memory stack to form an inter-polysilicon dielectric in EEPROM memory, and at the same time, form a thermal gate oxide in peripheral transistors used in the decoding logic of the EEPROM. (Candelier et al., “High Temperature Oxide (HTO) For Non-Volatile Memory Applications”, Microelectronic Engineering, Vol. 36, 1997, pp. 87-90; SGS Thompson-LETI.)
High-temperature oxide has also been used as the top oxide layer of an ONO memory stack, and as the gate oxide of high voltage periphery transistor. (See, U.S. Pat. No. 6,117,730) In this case, the bit line oxide is formed after the source/drain regions have been implanted, and after the silicon nitride layer of the ONO stack has been formed. Bit line oxide is consumed during bit line mask resist removal and during periphery strip mask resist removal. This consumption of the bit line oxide can result in a stressed oxybeak region. As a result, the charge-to-breakdown (Qbd) values of the fieldless array transistors are low even with the high temperature top oxide layer.
It would therefore be desirable to have an improved and cost effective integration scheme for embedding SONOS type multi-bit fieldless array transistors and high voltage logic transistors into the standard CMOS process flow.